The present invention relates to a dynamic shift register usin insulated-gate field-effect transistors of the same conductivity type and with the same method of control which requires for its operation two non-overlapping clock signals, i.e., a so-called two-phase MOS shift register. "MOS" is an abbreviation for "metal oxide semiconductor field-effect transistor", but is no longer limited exclusively to field-effect transistors with an oxide layer as the insulating layer lying below the gate terminal, because other insulating-layer materials have become known.
A subgroup of dynamic two-phase MOS shift registers is known, for example, from a book by D. Becker and H. Mader, "Hochintegrierte MOS-Schaltungen", Stuttgart 1972, page 126, FIG. 6-41. The shift register described there is a two-phase MOS shift register employing the so-called ratio technique. The term "ratio technique" in short means the following: Each of the two half stages of a shift-register stage contains an inverter consisting of a switching transistor and a load transistor. The series resistance of these two MOS transistors in the conducting state is dependent on the ratio of the channel width w to the channel length l. To ensure reliable operation, these ratios must be chosen to be different in the two inverter transistors, with the load transistor having a smaller w/l ratio than the switching transistor, i.e., the known dynamic two-phase MOS shift-register stage using the ratio technique has MOS transistors with different geometric layouts. In addition to the two clock signals, a dc voltage is necessary for operation.
Further subvarieties of dynamic MOS shift-register stages are known from the journal "The Electronic Engineer", March 1970, pages 59 to 61, FIG. 4 on page 60, for example, shows a shift-register stage described as being "ratioless", i.e. a two-phase MOS shift-register stage which dispenses with the above-mentioned choice of the ratios in the two inverter transistors. The inverter of that arrangement, however, consists of three series-connected MOS transistors, and this arrangement, too, requires a dc voltage in operation. Furthermore, suitable input capacitances of the two inverters must be chosen because the signal to be shifted is temporarily stored in these capacitances.
FIG. 6 on page 60 shows a two-phase MOS shift-register stage which requires no dc voltage in operation, but the two series-connected inverter transistors of a half stage have their free ends connected to one of the clock signals.
All prior art two-phase MOS shift-register stages have in each half stage, in addition to the aforementioned inverter, a coupling transistor which, in the case of the first-mentioned reference, couples the output of the inverter of the first half stage to the input of the inverter of the second half stage, with the input to the shift-register stage connected to the gate terminal of the switching transistor of the inverter of the first half stage, and the output coupled to the output of the inverter of the second half stage via the latter's switching transistor.
The arrangements disclosed in the second-mentioned reference show that a shift-register stage can also be formed by an arrangement whose input is connected to the gate terminal of the inverter of one half stage via the switching transistor of this half stage, while the output of the shift-register stage is coupled directly to the output of the inverter of the second half stage.
The known shift-register stages are universally applicable and can process any digital signal sequence, i.e., for example, a signal sequence in which the binary state HI, defined by a high potential, is followed in the next stage by such a state, too. At the end of a cycle of the two clock signals which are inverse to each other and do not overlap, this binary information has traveled from the input to the output of such a shift-register stage. To accomplish this shifting of the information, the inverter connected to the input inverts the signal and passes it to the gate terminal and to the input capacitance (see above) of the inverter of the second half stage during the first half cycle of the clock signal, and the second inverter inverts this signal again and passes it to the output during the second half cycle of the clock signal. The signal to be shifted thus appears at the output twice inverted, i.e., with the correct polarity.
If, in certain applications, it is necessary to be able to take off the signal with the correct polarity after the first clock-signal half cycle, i.e. in non-inverted form, it turns out that the known to-phase MOS shift-register stages cannot meet this requirement. It would be possible in principle to provide at the output of the first half stage an inverter which reinverts the inverted signal, so to speak; the time position of this reinverted signal would, however, be such that overlapping with the undelayed signal would be the inevitable consequence. The above-mentioned requirement can be met with the known two-phase MOS shift-register stages only by doubling the frequency of the clock signals and the number of shift register stages, i.e., forming from two adjacent shift-register stages a "new" shift-register stage at whose center the non-inverted signal can be taken off without overlap after one half cycle of the clock signal, as intended. The amount of circuitry required for this is obviously considerable.